Recently techniques have been developed for a channel adaptive recovery of data from optical recording media. However, due to the multitude of possible media types, e.g. Compact Disk, Digital Versatile Disk, Blu-ray Disk, and many other types, and the fact that some recording media types are not protected by a housing, a stronger monitoring of the adaptive processes is required. For this purpose several solutions were proposed to implement a reliable data retrieval processing. One solution is depicted in FIG. 1. A high frequency data stream HF captured from a recording medium is sampled and quantized in an analog-to-digital converter 1, resampled to the data channel clock rate by a sample rate converter 4, and fed to a bit recovery block 11 dealing with the channel adaptation. The channel clock for the resampling is recovered in a clock recovery block 10, which typically includes a phase locked loop 3 preceded by an equalizer 2. The data for this equalizer 2 is either received directly from the analog-to-digital converter 1 or as phase information from the bit recovery block 11. The obtained data and the clock are transmitted to a demodulator 9, which sends the demodulated data to error correction processing (to ECC).
The bit recovery block includes an adaptive equalizer 8 and an associated coefficient updating block 7, which uses the least mean square (LMS) algorithm and weights the output of the adaptive equalizer 8 with the recovered data after filtering by a target filter 5. Due to the increased intersymbol interference of current modulation schemes for channels of optical recording media a partial response maximum likelihood detector 6 is provided for detecting the most likely data from the incoming data stream. Since the channel modulation generally uses a run-length limited coding scheme it is common to employ a Viterbi decoder 6.
More recently it has been proposed to provide an adaptive Viterbi detector 14 as shown in FIG. 2. In this case, while monitoring the output of the Viterbi detector 15, i.e. the recovered data bits, the target values against which the likelihood of the possible data bit is measured are updated by a target value updating block 17. This is realized by comparing a best case value, i.e. the most likely value, with the data fed into the adaptive Viterbi decoder 15. A slicer 12 is provided for roughly eliminating DC components, which are not caused by the modulation but by data coupling. This is the digital counterpart of a decoupling capacitor trimmed for the lowest frequencies. The higher order DC component caused by the modulation changes on run-length time frames and is tackled in the equalizer 8. A state detector 16 follows the Trellis diagram of the Viterbi decoder 15 by monitoring the bit combinations. The Trellis diagram will be explained further below with reference to FIG. 9. For example, the subsequently detected bits ‘++−’ (i.e. bit order ‘1 1 0’ or state ‘4’) only allow a transition to a following state ‘3’. From state ‘2’ the transition may be to states ‘4’ and ‘5’. If an invalid transition is detected in the target update block 17 this target is not updated with the value of the corresponding input sample, which should actually give a closer match to the correct signal.
However, adaptive processes tend to become unstable and counteractive under certain circumstances like initialization or when dealing with errors in the data stream caused by scratches or fingerprints. Therefore, it has been proposed to introduce an auxiliary detector 20 to improve the adaptation performance of the bit recovery block 11 under such conditions and to meet high speed data detection requirements. A scheme of such an arrangement is shown in FIG. 3. The auxiliary detector 20 includes a pre-equalizer 21, a data pre-slicer 22, a non-linear equalizer 23, and a bit detector 24. This auxiliary detector 20 basically slices the bit information out of the center of the resampled hf data. The detector 20 has certain limitations considering run-length dependent parasitic DC-components, and tends to misdetect the shorter run-length data bits. Nevertheless, the auxiliary detector 20 outperforms the Viterbi detector 14 when dealing with corrupted data regions on a recording medium and does not have the detection latency immanent to the filter length and path memory depth used in the Viterbi bit detection path 14. An event logic 25 as indicated in FIG. 3 decodes the data sample transition as above zero, zero or below zero and passes this information to the clock recovery block 10 (not shown here) together with the corresponding phase value.
When dealing with several types of recording media and channels (e.g. DVD+RW, DVD-RW etc.) a high degree of flexibility is required for the adaptation processes. Some flexibility can still only be provided by a system reconfiguration initiated by a host control, but some flexibility is already within the scope of hardware implementation, due to the increased integration level of very large scale integrated circuits (VLSI).
It is an object of the present invention to provide an improved arrangement for adaptive bit recovery allowing a reliable bit detection exceeding the performance of common data detection processors.